/**
 @file sys_usw_eunit.h

 @date 2019-10-14

 @version v1.0

*/
#ifndef _SYS_USW_EUNIT_H
#define _SYS_USW_EUNIT_H
#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_debug.h"
#include "ctc_chip.h"
#include "ctc_eunit.h"
#include "sal_task.h"
#include "sal_mutex.h"


#define SYS_EUNIT_DBG_OUT(level, FMT, ...) \
    CTC_DEBUG_OUT(chip, eunit, EUNIT_SYS, level, FMT, ## __VA_ARGS__)

#define SYS_EUNIT_RUN_STATUS_INIT 0
#define SYS_EUNIT_RUN_STATUS_RUNNING 1
#define SYS_EUNIT_RUN_STATUS_SUSPEND 2

#define SYS_EUNIT_TBL_RW_MAX_LEN 64

#define SYS_EUNIT_CMD_TIMEOUT 5000
#define SYS_EUNIT_APP_NAME_LEN_MAX    15

/*for tmm*/
#define M_UNTT_TOD_ENABLE   0
#define M_UNTT_SYNC_ENABLE  1
#define M_UNTT_MAX_NUM   7

typedef enum sys_eunit_type_e
{
    SYS_EUNIT_E = 0,
    SYS_EUNIT_S,
    SYS_EUNIT_M,

    SYS_EUNIT_MAX
}sys_eunit_type_t;


enum sys_eunit_tsx_type_e
{
    SYS_EUNIT_TSX_MAC_STATS = 0,
    SYS_EUNIT_TSX_DROP_STATS = 1,
    SYS_EUNIT_TSX_BUFFER_WATERMARK = 2,
    SYS_EUNIT_TSX_LATENCY_WATERMARK = 3,
    SYS_EUNIT_TSX_TYPE_MAX
};
typedef enum sys_eunit_tsx_type_e sys_eunit_tsx_type_t;


typedef struct sys_eunit_tsx_cfg_s
{
    uint32 dest_map : 19;
    uint32 type : 5;  /*sys_eunit_tsx_type_t*/
    uint32 dest_map_valid : 1;
    uint32 nh_ptr_valid : 1;
    uint32 type_valid : 1;
    uint32 port_bmp_valid : 1;
    uint32 interval_valid : 1;
    uint32 enable_valid : 1;
    uint32 enable : 1;
    uint32 rsv1 : 1;

    uint32 nh_ptr : 18;
    uint32 nh_ext : 1;
    uint32 rsv2 : 13;

    uint32 process_cnt;
    uint32 nh_id;
    uint32 interval;
    uint32 phy_port_bmp[CTC_PORT_BITMAP_IN_WORD];
}sys_eunit_tsx_cfg_t;

enum sys_eunit_tex_type_e
{
    SYS_EUNIT_TEX_DROP_EVENT = 0,
    SYS_EUNIT_TEX_TYPE_MAX
};
typedef enum sys_eunit_tex_type_e sys_eunit_tex_type_t;

enum sys_eunit_mox_type_e
{
    SYS_EUNIT_MOX_DROP_EVENT = 0,
    SYS_EUNIT_MOX_TYPE_MAX
};
typedef enum sys_eunit_mox_type_e sys_eunit_mox_type_t;

typedef struct sys_eunit_tex_cfg_s
{
    uint32 dest_map : 19;
    uint32 type : 5;
    uint32 dest_map_valid : 1;
    uint32 nh_ptr_valid : 1;
    uint32 type_valid : 1;
    uint32 enable_valid : 1;
    uint32 enable : 1;
    uint32 cpu_reason_valid : 1;
    uint32 rsv1 : 2;

    uint32 nh_ptr : 18;
    uint32 nh_ext : 1;
    uint32 cpu_reason : 10;
    uint32 rsv2 : 3;
    uint32 process_cnt;
    uint32 nh_id;
}sys_eunit_tex_cfg_t;

typedef struct sys_eunit_mox_cfg_s
{
    uint32 dest_map : 19;
    uint32 type : 5;
    uint32 dest_map_valid : 1;
    uint32 nh_ptr_valid : 1;
    uint32 type_valid : 1;
    uint32 enable_valid : 1;
    uint32 enable : 1;
    uint32 rsv1 : 3;

    uint32 nh_ptr : 18;
    uint32 nh_ext : 1;
    uint32 rsv2 : 13;
    uint32 process_cnt;
}sys_eunit_mox_cfg_t;

typedef struct sys_eunit_ifa_cfg_s
{
    uint32 protocol : 8,
           cpu_reason : 10,
           session_id : 5,
           protocol_valid : 1,
           cpu_reason_valid : 1,
           node_valid : 1,
           gns_valid : 1,
           max_length_valid : 1,
           hop_limit_valid : 1,
           req_vec_valid : 1,
           session_id_valid : 1,
           rsv : 1;

    uint32 node : 4,
           gns  : 4,
           max_length : 8,
           hop_limit  : 8,
           req_vec    : 8;
    uint32 nh_ptr     : 18,
           nh_ext     : 1,
           nh_ptr_valid : 1,
           rsv1       : 12;
    uint32 dest_map   : 19,
           dest_map_valid   : 1,
           ifa_en     : 1,
           ifa_en_valid : 1,
           rsv2       : 10;
}sys_eunit_ifa_cfg_t;


struct sys_eunit_ptp_cfg_s
{
    uint32 tx_en : 16;
    uint32 rx_en : 16;

    /*default ds*/
    uint8  clock_identity[8];
    uint32 is_two_step : 1;
    uint32 domain_num : 8;
    uint32 event_destmap : 19;
    uint32 rsv : 4;

    uint32 speed;
    uint32 mc_mac_valid0;
    uint32 mc_mac_valid1;

    /*parent ds*/
    uint8  parent_clock_id[8];

    uint16 parent_port_num;
    uint16 lport;

    uint32 param_valid : 1;
    uint32 report_ts_en : 1;
    uint32 session_id:8;
    uint32 general_nh_ptr  :18;
    uint32 set_syncIntf_prama :1;
    uint32 ext_adjust_en : 1;
    uint32 session_enable : 1;
    uint32 rsv1 : 1;

    /*port ds*/  
    int8 sync_interval : 8;
    int8 delay_req_interval : 8;
    int8 pdelay_req_interval : 8;
    int8 rsv2;

    uint32 report_msg_en : 16;
    uint32 source_port_id :16;
    
    uint32 version_id : 2;
    uint32 event_nh_ptr : 18;
    uint32 ext_len : 2;
    uint32 domain_id :1;
    uint32 mac_id : 9;

    uint32 general_destmap : 19;
    uint32 rsv3 : 13;

    /*stats*/
    uint32 tx_stats[16];
    uint32 rx_stats[16];
    uint32 drop_stats[16];

    uint32 syncIntf_cfg;

};
typedef struct sys_eunit_ptp_cfg_s sys_eunit_ptp_cfg_t;

enum sys_eunit_cfg_type_e
{
    SYS_EUNIT_CFG_TSX,
    SYS_EUNIT_CFG_TEX,
    SYS_EUNIT_CFG_MOX,
    SYS_EUNIT_CFG_G8031,
    SYS_EUNIT_CFG_NPM_IM,
    SYS_EUNIT_CFG_IFA,
    SYS_EUNIT_CFG_PTP_DOMAIN_0,
    SYS_EUNIT_CFG_PTP_DOMAIN_1,
    SYS_EUNIT_CFG_SWITCH_ID, /*use MiscExtInfo0/ScpuMiscExtInfo0 */
    SYS_EUNIT_CFG_LED,
    SYS_EUNIT_CFG_LED_MAPPING,
	SYS_EUNIT_CFG_LEARNING_AGING,
    SYS_EUNIT_CFG_SENSOR_MONITOR,
    SYS_EUNIT_CFG_HW_RESET,
    SYS_EUNIT_CFG_TOD,
    SYS_EUNIT_CFG_APP_STATUS,
    SYS_EUNIT_CFG_USER_CFG,

    SYS_EUNIT_CFG_MAX
};
typedef enum sys_eunit_cfg_type_e sys_eunit_cfg_type_t;

struct sys_eunit_npm_im_s
{
    uint32 interval_thrd : 10,
           profile_id : 13,
           enable : 1,
           type : 3,
           rsv : 5;
};
typedef struct sys_eunit_npm_im_s sys_eunit_npm_im_t;


#define SYS_EUNIT_CFG_CMD_NAME_LEN 128
enum sys_eunit_cfg_op_type_e
{
    SYS_EUNIT_CFG_OP_GET = 0,
    SYS_EUNIT_CFG_OP_SET = 1
};
typedef enum sys_eunit_cfg_op_type_e sys_eunit_cfg_op_type_t;

struct sys_eunit_cfg_cmd_s
{
    uint32 valid    : 1;
    uint32 done     : 1;
    uint32 op       : 3;        /*ctc_cfg_op_type_t*/
    uint32 type     : 10;       /* sys_eunit_cfg_type_t */
    uint32 status   : 5;        /*error status*/
    uint32 data_len : 12;       /*max value: 1024 (Bytes)*/
    uint32 eunit_id : 3;        /* for eunit simulation, pass eunit_id */
    uint32 srv      : 29;
    char   data[0];             /*refer to user config data, size must be multi of 4 Bytes*/
};
typedef struct sys_eunit_cfg_cmd_s sys_eunit_cfg_cmd_t;

struct sys_eunit_learning_aging_cfg_s
{
    uint32 enable : 1;
    uint32 conflict_sync_en : 1;
    uint32 conflict_fifo_depth : 12; /*max : 1024*/
    uint32 enable_valid : 1;
    uint32 conflict_sync_en_valid : 1;
    uint32 conflict_fifo_depth_valid : 1;
    uint32 fifo_intr_cnt : 6;
    uint32 fifo_intr_cnt_valid : 1;
    uint32 rsv    : 8;
    uint32 aging_cnt;
    uint32 learn_cnt;
};
typedef struct sys_eunit_learning_aging_cfg_s sys_eunit_learning_aging_cfg_t;

struct sys_usw_eunit_tbl_rw_s
{
	uint32 addr;
	uint16 oper_bmp;
	uint16 len;
	uint32 status: 16;
	uint32 with_mask :1;
	uint32 rsv: 15;
	uint32 data[SYS_EUNIT_TBL_RW_MAX_LEN];
};
typedef struct sys_usw_eunit_tbl_rw_s sys_usw_eunit_tbl_rw_t;

enum sys_usw_eunit_tbl_rw_type_e
{
	SYS_USW_EUNIT_TBL_RW_TYPE_READ = 0,
	SYS_USW_EUNIT_TBL_RW_TYPE_WRITE = 1,
	SYS_USW_EUNIT_TBL_RW_TYPE_WITH_MASK = 2,

	SYS_USW_EUNIT_TBL_RW_TYPE_MAX
};
typedef enum sys_usw_eunit_tbl_rw_type_e sys_usw_eunit_tbl_rw_type_t;

struct sys_eunit_dma_info_s
{
    uint32 ring_bmp : 31;
    uint32 dma_sel  : 1;
    uint16 desc_cur_idx[32];
    uint32 ring_bmp_cross_core : 31;
    uint32 dma_sel_cross_core  : 1;
    uint16 desc_cur_idx_cross_core[32];
};
typedef struct sys_eunit_dma_info_s sys_eunit_dma_info_t;

typedef struct sys_eunit_port_info_s
{
    uint32 mac_id : 10; /*0-323, 320-323 CPUMAC*/
    uint32 mac_num : 5; /*800G: mac_num=8, 400G: mac_num=4, 200G:mac_num=2, <100G:mac_num=1, */
    uint32 valid : 1;
    uint32 rsv : 16;
} sys_eunit_port_info_t;

/*config receive structure*/
typedef struct sys_eunit_config_port_info_s
{
    uint8  lport_num; /*<32*/
    uint8  rsv[3];
    uint16 lport[32];
    sys_eunit_port_info_t info[32];
}sys_eunit_config_port_info_t;

struct sys_eunit_peri_led_cfg_s
{
    uint32 mac_led_num : 10;
    uint32 led_num    : 10;
    uint32 lport_en   : 1;
    uint32 rsv        : 11;
};
typedef struct sys_eunit_peri_led_cfg_s sys_eunit_peri_led_cfg_t;

struct sys_eunit_peri_led_mapping_s
{
    uint16 led_id;
    uint16 port_id;
};
typedef struct sys_eunit_peri_led_mapping_s sys_eunit_peri_led_mapping_t;

typedef struct sys_eunit_emic_ver_s
{
    int8 version[20];
    int8 date[20];
}sys_eunit_emic_ver_t;

typedef struct sys_eunit_mem_info_s
{
    uint32 total;
    uint32 ram_used;
    uint32 ram_used_max;
}sys_eunit_mem_info_t;

struct sys_eunit_peri_sensor_cfg_s
{
    uint32 interval;
    uint16 on_thrd;
    uint16 off_thrd;
    uint32 sensor_bmp;
    uint32 sensor_value[CTC_MAX_CHIP_SENSOR];
    uint32 sensor_process_cnt[CTC_MAX_CHIP_SENSOR];
    uint32 sensor_event_bmp;
    uint8 type;
    uint8 state;
    uint8 rsv[2];
};
typedef struct sys_eunit_peri_sensor_cfg_s sys_eunit_peri_sensor_cfg_t;

typedef enum sys_usw_eunit_isr_type_e
{
    SYS_EUNIT_ISR_HEART = 0,
    SYS_EUNIT_ISR_ERROR,
    SYS_EUNIT_ISR_G8031,
    SYS_EUNIT_NPM_IM,
    SYS_EUNIT_ISR_CODE_READY,/*for misc mcpu*/
    SYS_EUNIT_ISR_PTP,
    SYS_EUNIT_ISR_PTP_0 =16,
    SYS_EUNIT_ISR_PTP_1,
    SYS_EUNIT_ISR_G8031_MIS_GRP0 = 32,
    SYS_EUNIT_ISR_G8031_MIS_GRP1,
    SYS_EUNIT_ISR_G8031_MIS_GRP2,
    SYS_EUNIT_ISR_G8031_STATE_CHANGE_GRP0 = 35,
    SYS_EUNIT_ISR_G8031_STATE_CHANGE_GRP1,
    SYS_EUNIT_ISR_G8031_STATE_CHANGE_GRP2,
    SYS_EUNIT_ISR_G8031_STATE_APS_SWITCH_GRP0 = 38,
    SYS_EUNIT_ISR_G8031_STATE_APS_SWITCH_GRP1,
    SYS_EUNIT_ISR_G8031_STATE_APS_SWITCH_GRP2,
    SYS_EUNIT_ISR_SENSOR_MONITOR,
    SYS_EUNIT_ISR_TOD_CODE_READY,

    SYS_EUNIT_ISR_MAX
}sys_usw_eunit_isr_type_t;

typedef enum sys_eunit_lock_id_e
{
    SYS_EUNIT_LOCK_ID_FIBACC = 0,
    SYS_EUNIT_LOCK_ID_SENSOR = 1,

    SYS_EUNIT_LOCK_ID_MAX = 7
}sys_eunit_lock_id_t;

struct sys_usw_eunit_isr_data_s
{
    uint8 unit;
    uint8 irq_id;
};
typedef struct sys_usw_eunit_isr_data_s sys_usw_eunit_isr_data_t;
typedef int32 (* sys_usw_eunit_isr_t)(uint8 lchip, uint8 isr_type, void* p_data);

typedef struct sys_eunit_cpu_reason_info_s
{
    uint16 reason_group;
    uint8  queue_id;  /*start queue_id*/
    uint8  queue_num;
}sys_eunit_cpu_reason_info_t;


typedef struct sys_usw_eunit_master_s
{
    sal_mutex_t* mutex;
    sys_usw_eunit_isr_t* isr;
    uint32 reset_times[SYS_EUNIT_MAX];
    uint8 eunit_la_id; /*learinig_aging*/
}sys_usw_eunit_master_t;


typedef struct sys_usw_eunit_status_params_s
{
    uint8 eunit_id;
    uint8 app_id;
}sys_usw_eunit_status_params_t;

typedef struct sys_usw_eunit_app_info_hdr_s
{
    uint32  app_num        :8;    /* cfg max app num */
    uint32  current_idx    :8;    /* current num */     
    uint32  app_name_len   :8;
    uint32  rsvd           :8;
}sys_usw_eunit_app_info_hdr_t;

typedef struct sys_usw_eunit_keepalive_body_s
{
    uint32 install      : 1;   /* indicate if app is installed */
    uint32 alive_cnt    : 31;  /* app alive cnt*/
}sys_usw_eunit_keepalive_body_t;

typedef struct sys_usw_eunit_dbg_hdr_s
{
    uint32 cnt  : 10;
    uint32 size : 12;
    uint32 line : 10; /*info line */
}sys_usw_eunit_dbg_hdr_t;

struct sys_usw_eunit_thread_info_s
{
    char name[32];
    uint8 stat;
    uint8 priority;
    uint16 stack_size;
    /* stack point and entry */
    uint32 sp;                                     /**< stack point */
    uint32 stack_addr;                             /**< stack address */
};
typedef struct sys_usw_eunit_thread_info_s sys_usw_eunit_thread_info_t;

struct sys_usw_eunit_thread_info_list_s
{
    uint8 info_num;
    uint8 rsv[3];
    sys_usw_eunit_thread_info_t info[8]; /*max 8*/
};
typedef struct sys_usw_eunit_thread_info_list_s sys_usw_eunit_thread_info_list_t;

typedef struct sys_usw_eunit_app_info_body_s
{
    uint8  app_id;
    char   app_name[SYS_EUNIT_APP_NAME_LEN_MAX];
}sys_usw_eunit_app_info_body_t;


#if defined E_UNIT && (FEATURE_MODE == 0)
extern int32
sys_usw_eunit_hw_lock(uint8 lchip, uint8 unit, uint8 lock_id);

extern int32
sys_usw_eunit_hw_unlock(uint8 lchip, uint8 unit, uint8 lock_id);

extern int32
sys_usw_eunit_get_hw_lock(uint8 lchip, uint8 type, uint8* unit, uint8* lock_id);

extern int32
sys_usw_eunit_set_cfg(uint8 lchip, uint8 type, void* p_cfg);

extern int32
sys_usw_eunit_get_cfg(uint8 lchip, uint8 type, void* p_cfg);

extern int32
sys_usw_eunit_get_unit_id(uint8 lchip, uint8 type, uint8* uint);

extern int32
sys_usw_eunit_regitser_isr(uint8 lchip, uint8 isr_type, sys_usw_eunit_isr_t isr);

extern int32
sys_usw_eunit_show_status(uint8 lchip, uint8 level, void* p_params);

extern int32
sys_usw_eunit_reset(uint8 lchip, uint8 unit, ctc_eunit_install_t* p_eunit);

extern int32
sys_usw_eunit_init(uint8 lchip);

extern int32
sys_usw_eunit_deinit(uint8 lchip);

extern int32
sys_usw_eunit_get_cpu_reason_info(uint8 lchip, uint8 eunit_id, sys_eunit_cpu_reason_info_t* p_info);

extern int32
sys_usw_eunit_lock_cb(uint8 lchip, uint8 lock_type, uint8 status);

extern int32
sys_usw_eunit_get_usr_config_cmd(uint8 lchip, void* p_value);

extern int32
sys_usw_eunit_set_usr_config_cmd(uint8 lchip, void* p_value);

extern int32
sys_usw_eunit_get_app_alive_cnt(uint8 lchip, void* p_value);


#endif /*E_UNIT*/

#ifdef __cplusplus
}
#endif

#endif


